FPGA-enabled design for per-stream processing in asynchronous traffic shaping for TSN

The growing demand for deterministic communication in Industry 5.0 has reinforced the role of IEEE Time-Sensitive Networking (TSN) as the backbone of next-generation Ethernet. Traditional synchronous mechanisms face scalability and clock-drift issues, which IEEE 802.1Qcr mitigates through the Asynchronous Traffic Shaper (ATS). ATS regulates frame timing by computing eligibility times without clock alignment, ensuring low delay and deterministic performance across multiple traffic streams. This paper focuses on the metering phase of ATS, analyzing both per-stream eligibility computation and the resource utilization of metering modules as key factors to guarantee fairness and efficiency. We design a Field Programmable Gate Array (FPGA)-based implementation combining token bucket logic with ATS scheduling, enabling precise evaluation of delay, and hardware cost under realistic industrial workloads. Results show that per-stream ATS metering provides deterministic behavior while maintaining minimal hardware utilization, making the design well-suited for large-scale industrial environments.