SYCLARA: An open hardware-software platform for evaluating SYCL applications on RISC-V vector accelerators

Over the past few years, RISC-V has emerged as an open and extensible architecture with flexible vector extensions (RVV) for scaling computationally-intensive workloads. On the software side, SYCL has emerged as a standardized, cross-architecture programming

model that can provide performance portability across several accelerators. In this work, we describe our efforts to bring these two standards together by extending the integration of CVA6 RISC-V core with the ARA2 RVV implementation to enable SYCL kernel

offload via the oneAPI Construction Kit.