Open, cross-architecture acceleration of data analytics with SYCL and RISC-V

Kabadzhov, Ivan Donchev; Mordgado, Jose; Ilic, Aleksandar; Appuswamy, Raja
EURO-PAR 2025, 31st International European Conference on parallel and distributed computing, 25-29 August 2025, Dresden, Germany / Also published in "Lecture Notes in Computer Science"

The past few years have witnessed the growth in popularity of two standards for accelerating AI and analytics. On the hardware front, the advent of RISC-V, an open instruction set architecture, has ushered in a new era in standards-based design and customization of microprocessors. On the programming front, SYCL has emerged as a cross-vendor, cross-architecture, data parallel programming model for all types of accelerators. In this work, we take the first steps towards bringing these two standards together to enable a new line of work on fully-open, vendor-neutral, cross-architecture-accelerated database engines by developing SYCLDB--a SYCL-based library of key relational operations that works together with the oneAPI Construction Kit (OCK) to target multi-vendor CPU and accelerator backends. Using SYCLDB, we perform a comparative evaluation with micro and macrobenchmarks to show that SYCLDB can (i) exploit vectorization provided by RVV accelerators, (ii) provide performance on-par with CUDA counterparts on NVIDIA GPUs, and (iii) exploit multithreading in x64 and RISC-V CPUs, all the while using a single code base.


Type:
Conférence
City:
Dresden
Date:
2025-08-25
Department:
Data Science
Eurecom Ref:
8333
Copyright:
© Springer. Personal use of this material is permitted. The definitive version of this paper was published in EURO-PAR 2025, 31st International European Conference on parallel and distributed computing, 25-29 August 2025, Dresden, Germany / Also published in "Lecture Notes in Computer Science" and is available at :

PERMALINK : https://www.eurecom.fr/publication/8333